1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device formed on an insulating film and its manufacturing method.
2. Description of the Background Art
To enhance the performance of a semiconductor, it has been attempted to manufacture a semiconductor integrated circuit of a small floating capacity by separating a circuit element by a dielectric. Generally, in a manufacturing method of semiconductor, a so-called LOCOS method is employed for separating a circuit element. Each transistor separated in this separating method is formed in a completely insulated semiconductor layer, and hence it is reported to have many benefits, such as freedom from effect of latch-up with adjacent transistor.
FIG. 66 to FIG. 90 are sectional views showing such conventional manufacturing method of semiconductor in the sequence of steps.
First, as shown in FIG. 66, a semiconductor layer 21 on an insulating film 20 is oxidized in a wet atmosphere at about 950.degree. C., and an oxide film 22 is formed in a thickness of 300 angstroms. On this oxide film 22, further, a nitride film 23 is formed in a thickness of 500 angstroms by CVD method (FIG. 66).
Next, as shown in FIG. 67, applying a resist 249a, it is patterned in a desired shape. Then, by dry etching, the nitride film 23 and oxide film 22 are removed. Consequently, as shown in FIG. 68, a resist 249b is patterned (double coated) only in a region for forming a PMOS transistor (hereinafter PMOS region), and boron ions are implanted in a region for forming an NMOS transistor (hereinafter NMOS region). The boron implantation amount is 3.times.10.sup.13 /cm.sup.2, and the implantation energy is 20 keV. By this implantation, a high concentration impurity region 206 is formed in the semiconductor layer 21 (edge region of active layer) of the NMOS region not covered with the nitride film 23. Then the resists 249a, 249b are removed (FIG. 69).
By oxidizing the semiconductor layer 21 in wet atmosphere for 60 minutes at 950.degree. C., an oxide film 25 is formed (hereinafter such oxide film forming technique is mentioned as LOCOS oxidation). At this time, the nitride film 23 is used as mask when oxidizing, and the oxide film 25 is formed only in the region not covered with it (FIG. 70). The nitride film 23 is then removed by hot phosphoric acid in the condition of 160.degree. C. and 30 minutes (FIG. 71).
Next, as shown in FIG. 72, a resist 249c is formed only in the PMOS region, and boron ions are implanted in the NMOS region. The implantation energy is 20 keV, and the implantation amount is 3.times.10.sup.12 /cm.sup.2. This implantation is for channel doping, and is applied for setting the threshold voltage of the NMOS transistor. Afterwards, the resist 249c is removed.
Similarly, forming a resist 249d in the NMOS region, boron ions are implanted in the PMOS region by 3.times.10.sup.11 /cm.sup.2 with an energy of 20 keV. This ion implantation is intended to set the threshold voltage of the PMOS transistor.
Removing the resist 249d, polysilicon 27 containing phosphorus at 10.times.10.sup.19 /cm.sup.3 is formed in a thickness of 3000 angstroms, and a resist 249e is patterned on the polysilicon 27 in a shape of gate wiring (FIG. 74). Using the resist 249e as mask, the polysilicon 27 is etched and gate wiring is obtained, and then the resist 249e is removed (FIG. 75).
Forming a resist 249f in the PMOS region, phosphorus ions are implanted in the NMOS region by 1.times.10.sup.14 /cm.sup.2 with an energy of 20 keV. As a result, an N.sup.- region 30 is formed in the NMOS region (FIG. 76). Removing the resists 249f, a resist 249g is formed in the NMOS region. In the PMOS region, boron ions are implanted by 1.times.10.sup.13 /cm.sup.2 with an energy of 20 keV, and a P.sup.- region 31 is formed in the PMOS region (FIG. 77). These ion implantations are intended to form LDD regions for the NMOS transistor and PMOS transistor, respectively.
Removing the resist 249g, as shown in FIG. 78, an oxide film 32 formed by using TEOS (tetraethyl orthosilicate) (hereinafter TEOS film) is formed in a thickness of 1500 angstroms. When it is removed by dry etching in a strong anisotropic gas atmosphere, the TEOS film 32 is left over in a width of 1500 angstroms only on the side wall of the polysilicon 27 left over as gate wiring (FIG. 79).
Consequently, as shown in FIG. 80, forming a resist 249h in the PMOS region, arsenic ions are implanted in the NMOS region by 4.times.10.sup.15 /cm.sup.2 with an energy of 20 keV. As a result, an N.sup.+ region 33 is formed. Removing the resist 249h, a resist 249i is formed in the NMOS region. In the PMOS region, boron ions are implanted by 5.times.10.sup.15 /cm.sup.2 with an energy of 20 keV, and a P.sup.+ region 34 is formed. By these ion implantations, source/drain regions are formed in the NMOS transistor and PMOS transistor, respectively.
Removing the resist 249i (FIG. 82), a Ti film 35 is sputtered in a thickness of 200 angstroms (FIG. 83). By lamp annealing for 30 seconds at 700.degree. C., a compound 36 of silicon and titanium is formed only on the N.sup.+ region 33 and P.sup.+ region 34 which are source/drain regions. Removing the unreacted Ti film 35, lamp annealing is repeated at 950.degree. C. for 30 seconds. The compound 36 is stabilized by this lamp annealing (FIG. 84).
Then, as shown in FIG. 85, a TEOS film 37 is formed in a thickness of 1500 angstroms. Applying a resist 249j, it is patterned to open a region for removing the TEOS film 37, that is, a contact region on the N.sup.+ region 33 and P.sup.+ region 34 (FIG. 86). Using the resist 249j as mask, the TEOS film 37 is removed by dry etching, and the compound 36 in the contact region is exposed (FIG. 87).
On the entire surface of the structure thus obtained, an aluminum film 39 is formed (FIG. 88). As shown in FIG. 89, consequently, patterning a resist 249k in a wiring shape, the aluminum film 39 is patterned by dry etching. FIG. 90 is a sectional view of the CMOS transistor completed in this process.
Thus formed NMOS transistor should, by nature, present an ideal sub-threshold characteristic. However, a parasitic transistor is formed in the edge of the oxide film 25 obtained by LOCOS oxidation. This is because, as shown in FIG. 69 to FIG. 71, the boron ions implanted in the semiconductor layer 21 as SOI layer are not diffused into the inside of the semiconductor 21 functioning as channel in LOCOS oxidation at 950.degree. C., but are sucked into the oxide film 25, thereby lowering the boron ion concentration of the semiconductor layer 21 near the oxide film 25.
When a parasitic transistor is formed around the SOI active layer in this way, instead of presenting the desired transistor characteristic, a hump is formed in the sub-threshold characteristic.